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  • Technical Marketing Director
  • department of techno...
  • Shanghai
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category:Technical
Working place:Shanghai Hands-on background:/

Post duties:

1.Develops abstract scope business & marketing plans, assesses market penetration and product positioning to drive competitive advantage, revenue and market share

2.Recommends investment decisions for new product development

3.Conducts abstract competitive analysis for specific products or product lines.

4. Assists with abstract pricing strategies to build and protect a leadership position in market share while enhancing profit margins and developing marketing tools for successful product introductions

5.Partners with Engineering, Manufacturing and Sales to develop new products and enhance existing products as well as communicate critical market needs and time requirements

6.Understands technical and business environments. Assists with the development of strategies to meet business objectives

7.Manages release of abstract products through the end of their product life cycle

Tenure requirements:

1.Rich experience in consumer and industrial ASIC marketing is a must.

2.Regarded as the technical expert in their particular field

3.Demonstrates in-depth and/or breadth of expertise in own discipline and broad knowledge of other disciplines within the function

4.  Anticipates business and regulatory issues; recommends product, process or service improvements

5.Leads projects with notable risk and complexity; develops the strategy for project execution

6.Solves unique and complex problems with broad impact on the business; requires conceptual and innovative thinking to develop solutions

7.Impacts the direction and resource allocation for program, project or services; works within general functional policies and industry guidelines

8.Communicates complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view

  • System Application SW Engineers/Manager
  • department of techno...
  • Shanghai
  • 1
  • Undergraduate
salary: salary negotiable Nature of work:Full-time Position category:Technical
Working place:Shanghai Hands-on background:at least 8 years’ experience

Post duties:

1. System/IP bringup, test and debug for both FPGA and SOC.

2. Linux Kernel/BSP/Boot/Driver design/porting and delivery

3. Join AI System design and Provide System solution

4. Co-work/communicate with SOC design team, FW design team, Bringup and post silicon validation team, FPGA, Customer, 3rd partner.


Tenure requirements:

1. Master/Bachelor, for Manager, at least 8 years’ experience

2. Demonstrated embedded system understanding, including ASIC/FPGA SOC HW system and embedded SW system, have good knowledge and understanding of embedded SW system (linux/android) architecture (HW, FW, Driver, HAL, Midware, Framework, Kernel mode, user mode, application, QT, etc.)

3. Broad understanding of SW design & testing methodologies, tools, flows, could lead or join in multiple teams/engineers design and commit the code in parallel

4. Proven experience and knowledge/technology on at least 2 of flowing SW fields: Embedded Linux BSP/Boot/Driver design, Embedded Linux/Android/RTOS system/kernel and file system, Embedded Linux/Android application, Embedded/PC based SW tool development, etc.

5. Proven enough coding quanity and good coding style, documentation

6. Familiar with common code management and in-parallel design methodologies (code repositories or version control methodologies), for ex: Git, SVN, P4, etc.

7. Familiar with common SW design and check/debug platform/tool, for ex: Linux/Unix os, command line, shell, perl, tcl, python, coverity, gdb, Jtag, coresight, Jlink etc.

8. Have good experience on working with various of compilers, for ex: ARMCC, arm-none-eabi-gcc,arm-none-linux-gnueabi-gcc,arm-eabi-gcc , etc.

9. Familiar with at least one of the following protocol/interface or field and have related solid Driver/Framework design/debug experience on these interface or field: Gstreamer,USB2.0/3.0,DDR4/LPDDR4 or lower speed,MIPI, SD/eMMC,CAN,SPI/QSPI,Video Codec, ISP, etc

10. Familiar with various test/debug/measurement instrument: oscilloscope, logic analyzer, protocol analyzer, etc.  Have board level debug experience.

11. Familiar with ARM/DSP C/C++ program, Have ARM/DSP system debug experience. Familiar with ARM core and ARM architecture (ARMV7/V8 arch), for ex: MMU, D/I cache, interrupt, pipeline, etc.

12. Have proven Video related SOC ASIC bringup/post silicon experience would be a good plus.

13. Good teamwork,Good learning capability,Good English.


  • System Application FW Engineer/Manager
  • department of techno...
  • Shanghai
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category:Technical
Working place:Shanghai Hands-on background:at least 6 years’ experience

Post duties:

1. System/IP bringup, enablement, test and debug for both FPGA and SOC.

2. Delivery solid FW/Driver for System SW invoking

3. Join AI System design(HW&SW)

4. Co-work/communicate with SOC design team, System SW design team, Bringup and post silicon validation team, FPGA, Customer, 3rd partner.


Tenure requirements:

1. Master/Bachelor, for FW Manager, at least 6 years’ experience

2. Familiar with ARM/DSP C/C++ program, Have ARM/DSP SOC embedded programming and debug experience(non-os), if having OS (linux/rtos/etc.), driver and boot development experience, this would be a plus.

3. Familiar with at least one of the following protocol/interface or field and have related solid FW design/debug experience on these interface or field: USB2.0/3.0,DDR4/LPDDR4 or lower speed,MIPI, SD/eMMC,CAN,SPI/QSPI,Video Codec, ISP etc. HW circuit design and debug experience is a better plus for these interfaces.

4. Familiar with various test/debug/measurement instrument: oscilloscope, logic analyzer, protocol analyzer, etc.  Must Have board level debug experience.

5. Proven enough coding quanity and good coding style, documentation

6. Familiar with common code management and in-parallel design methodologies (code repositories or version control methodolog ies), for ex: Git, SVN, P4, etc.

7. Familiar with common SW design and check/debug platform/tool, for ex: Linux/Unix os, command line, shell, perl, tcl, python, coverity, gdb, Jtag, coresight, Jlink etc.

8. Have good experience on working with various of compilers, for ex: ARMCC, arm-none-eabi-gcc,arm-none-linux-gnueabi-gcc,arm-eabi-gcc , etc.

9. Familiar with ARM/DSP core and ARM/DSP architecture, for ex: MMU, D/I cache, interrupt, pipeline, etc. ,if familiar with AMBA bus(AXI,AHB,APB) and have knowledge on SOC's architecture, working modes, power domain/clock domain, and system application , this would be a plus.

10. Familiar with FPGA prototyping design would be a plus

11. Have proven Video related SOC ASIC bringup/post silicon experience would be a good plus.

12. Good teamwork,Good learning capability,Good English.

  • Bringup/Post silicon validation Engineer/Manager
  • department of techno...
  • Shanghai
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category:Technical
Working place:Shanghai Hands-on background:at least 8 years’ experience

Post duties:

1. Design ASIC SOC System/IP bringup/validation plan, Design ASIC SOC Power/Performance/Yield optimization plan

2. Lead or Responsible for ASIC SOC bringup/validation/optimization solution/architecture design and ASIC SOC validation Platform design, requirement and interface definition, review the board schematic designed by board engineers.

3. ASIC SOC System/IP bringup, enablement, test, characterization, PVT/Electrical, and issue debug, etc.

4. ASIC SOC Power/Performance/Yield optimization and debug

5. Join AI System design(HW&SW)

6. Co-work or lead with other teams to achive post silicon sucessful(Issue resolved, Chip enabled and optimized, etc.) , which including SOC design team, System SW design team, FW team, operation team, etc.


Tenure requirements:

1. Master/Bachelor, for Bringup/Post silicon Manager, at least 8 years’ experience

2. Familiar with ARM/DSP whole system with various of IPs and peripherals, interface,etc. , Have good knowledge on SW/FW design, PCB design(schematic), ASIC/FPGA digital circuit, Analog IPs application(For ex: PLL, VCO, LDO, etc.), etc.

3. Have solid FPGA/ASIC SOC validation experience and proven System&HW&SW debug experience/skills,

4. Have good knowledge on Process, Yield, Power, performance, and have proven experience on analysis and optimize all of them for ASIC SOC project

5. Familiar with various validation methodologies, flow, tools, could design whole systems bringup&validation plan, including system and IP level function bringup/validation plan, plan for Power, performance, clock, stability, yield, compatibility, electrical, characterization, PVT, etc., could build whole validation/bringup system and platform.

6. Familiar with ARM/DSP C/C++ program, Have ARM/DSP SOC embedded programming and debug experience(non-os), if having OS (linux/rtos/etc.), driver and boot development experience, this would be a plus.

7. Familiar with at least one of the following protocol/interface or field : USB2.0/3.0,DDR4/LPDDR4 or lower speed,MIPI, SD/eMMC,CAN,SPI/QSPI, Video Codec, ISP, etc.

8. Familiar with various test/debug/measurement instrument: oscilloscope, logic analyzer, protocol analyzer, etc.  Must Have board level debug experience.

9. Familiar with ARM/DSP core and ARM/DSP architecture, familiar with AMBA bus (AXI, AHB, APB), have knowledge on various SOC's architecture, working modes, power domain/clock domain, and system application, etc.

10. Familiar with FPGA prototyping design and integration would be a plus

11. Have proven Video related SOC ASIC bringup/post silicon experience would be a good plus.

12. Good teamwork,Good learning capability,Good English.


  • FPGA Engineer
  • department of techno...
  • Shanghai
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category:Technical
Working place:Shanghai Hands-on background:Experience with HAPS is a plus

Post duties:

1. Develop and support FPGA design for SOC verification

2. Responsible for FPGA RTL coding, and migration from ASIC RTL to FPGA RTL

3. Responsible for FPGA synthesis/PR timing clean-up and bit file generation

4. Responsible for system and FPGA debug with signal probe tools


Tenure requirements:

1. Bachelor or above degrees in EE/Communication/CS majors

2. Must have experiences in digital logic design with Verilog/VHDL...etc.

3. Must have experiences with Xilinx Vertex/Spartan products and familiar with FPGA synthesis flows and tools (ISE, Vivado, Synplify, Chipscope, Protolink…etc)

4. Experience with DDR3/ARM/USB FPGA design is a plus.

5. Experience with HAPS is a plus.


  • Design for Test Engineer
  • department of techno...
  • Shanghai
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category:Technical
Working place:Shanghai Hands-on background:2+ years related experience required

Post duties:

1. Participate in SoC level DFT architecture definition.

2. Implement DFT strategy for the SoC chips, cooperating with design team

3. Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.

4. Develop the high coverage and cost effective test patterns.

5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.

6. Support other teams for DFT related problems.


Tenure requirements:

1. Either Bachelor or Master degree, 2+ years related experience required.

2. Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA

3. Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG.

4. Knowledge on and familiar with basic Mentor/ Synopsys DFT flow and tools

5. Proficient in Verilog/VHDL language

6. Be familiar with Shell/TCL/Perl program, or skilled in C program

7. Good English communication skills

8. Self-motivated and good team player


  • ASIC Design Engineer
  • department of techno...
  • Shanghai
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category:Technical
Working place:Shanghai Hands-on background:5+ years of working experiences in ASIC design

Post duties:

1. Understanding algorithm requirement and implement with verilog

2. System verification, debugging and performance analyzing

3. Building block level verification environment, writing block level test vectors.

4. Prepare architecture specification for IC circuits and assist in ensuring correct circuit implementation.

5. RTL coding to verify against circuit implementation; Perform integration into SOCs.

6. Verify functions by creating test cases, and modify test benches to work with internal simulation environment.

7. Develop test environments and analysis coverage.

8. Module and chip level synthesize with sdc/upf.

9. Assist with chip bring up and perform silicon functional/performance validation.

10. Define timing and power specifications, and identify timing solutions.

11. Assist with backend team on perform place-and-route and timing analysis of modules


Tenure requirements:

1. BS or above in EE or related

2. 5+ years of working experiences in ASIC design

3. Strong Verilog programming ability, familiar with mainstream of frond-end ASIC design flow & design tools

4. Perl, Shell and C++ scripting language is a must

5. Familiar with frontend integration flow

6. Strong problem solving and debugging skills

7. Knowledge of image processing is a plus

8. Good communication skills and strong team-player mindset

  • Digital Verification Engineer
  • department of techno...
  • Shanghai
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category:Technical
Working place:Shanghai Hands-on background: 3 years of work experience

Post duties:

1. Creating test plan according to design spec

2. Designing and developing verification environment;

3. Debugging SoC regression failure

4. Creating system checker/monitors and system UVCs, code & function coverage in SOC

5. Creating C test case running on ARM in SOC

6. Creating UVM test case in SOC


Tenure requirements:

1. Education and Experience-Bachelor or above with 3 years of work experience

2. Skills and Knowledge-

Verilog

System Verilo

UVM

Perl/Python/Tcl

AXI/AHB/APB

Co-sim between hardware and software is an additional plus

C/C++ is an additional plus

Lowpower/UPF/MIPI/USB/Ethernet/PCIE/SATA/SPI/I2C/etc. experience is an additional plus

ARM related experience is an additional plus


  • Firmware Engineer
  • department of techno...
  • Shanghai
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category: Technical
Working place:Shanghai Hands-on background:3 years' experience

Post duties:

1. Design and develop dual camera depth and neural network firmware on embedded system

2. Work with ASIC design team for the dual camera depth and neural network system performance and function validation including firmware/hardware co-simulation, FPGA verification, etc

3. Co-work closely with Software team to improve the framework of firmware, define and implement the API function and customize generic firmware to specific products

4. Analyze and fix bugs, and support customer-specific issues.


Tenure requirements:

1. Master degree with more than 3 years' experience or Bachelor degree with more than 5 years’ experience in related field

2. Strong C/C++ programming experience is required

3. Strong knowledge of ISP, Compute Visioin, Neural Network, etc

4. Knowledge of USB, MIPI, I2C, SPI, ARM

5. Experience to develop camera driver (in a certain platform such as Linux, Android, etc)

6. Good communication skills and strong team-player mindset

7. Experience on convolution neural network is a plus.


  • Physical Design Engineer
  • department of techno...
  • Shanghai
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category:Technical
Working place:Shanghai Hands-on background:3+year experience

Post duties:

1. Perform floor-planning, physical synthesis, clock tree and clock gating design, power gating, routing, layout, integration and physical verification

2. Solve deep sub-micron design problems such as leakage, power, signal integrity, DFM, DFT etc.

3. Independently assess and drive complex digital physical design projects

4. Enhance IC physical design flow methodology

5. Perform power, performance and area benchmark for new technology adoption

6. Develop Perl/TCL/Shell scripts for flow and procedure automation

7. Work proactively with EDA engineers and tool suppliers to debug tool functionality and bugs

8. Support failure analysis


Tenure requirements:

1. BS or above in Electrical Engineering with 3+year experience,

2. Complete knowledge of full design IC implementation and signoff process

3. Experienced with using Cadence Encounter, Synopsys ICC, ETS, Prime Time, PVS, QRC, Calibre, XRC, Hercules, StarRC etc.

4. Proficient in STA, power analysis, DRC/LVS/PEX/DFM, noise, static and dynamic IR drop analysis

5. Expertise in low power flow (power gating, multi-Vt, voltage islands, adaptive or dynamic voltage scaling etc)

6. Good UNIX background and Perl/Shell/SKILL scripting skills

7. Good written and verbal communication capability and proficient in both English and Mandarin

8. Strong time management and multi-tasking skills that enable on-time delivery

9. Analytical and persistent in resolving technical issues


  • Digital Verification Engineer
  • department of techno...
  • Suzhou
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category: Technical
Working place:Suzhou Hands-on background: 3 years of work experience

Post duties:

1. Creating test plan according to design spec

2. Designing and developing verification environment;

3. Debugging SoC regression failure

4. Creating system checker/monitors and system UVCs, code & function coverage in SOC

5. Creating C test case running on ARM in SOC

6. Creating UVM test case in SOC


Tenure requirements:

1. Education and Experience-Bachelor or above with 3 years of work experience

2. Skills and Knowledge-

Verilog

System Verilo

UVM

Perl/Python/Tcl

AXI/AHB/APB

Co-sim between hardware and software is an additional plus

C/C++ is an additional plus

Lowpower/UPF/MIPI/USB/Ethernet/PCIE/SATA/SPI/I2C/etc. experience is an additional plus

ARM related experience is an additional plus


  • Digital Verification Engineer (Leader/Engineers)
  • department of techno...
  • Suzhou
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category:Technical
Working place:Suzhou Hands-on background:3 years of work experience

Post duties:

1. Creating test plan according to design spec

2. Designing and developing verification environment;

3. Debugging SoC regression failure

4. Creating system checker/monitors and system UVCs, code & function coverage in SOC

5. Creating C test case running on ARM in SOC

6. Creating UVM test case in SOC


Tenure requirements:

1. Education and Experience-Bachelor or above with 3 years of work experience

2. Skills and Knowledge-

Verilog

System Verilo

UVM

Perl/Python/Tcl

AXI/AHB/APB

Co-sim between hardware and software is an additional plus

C/C++ is an additional plus

USB/Ethernet/PCIE/SATA/SPI/I2C/etc. experience is an additional plus


  • Technical Marketing Director
  • marketing department...
  • Shanghai
  • 1
  • Undergraduate
salary:salary negotiable Nature of work:Full-time Position category:Marketers
Working place:Shanghai Hands-on background:Rich experience in consumer and industrial ASIC marketing

Post duties:

1. Develops abstract scope business & marketing plans, assesses market penetration and product positioning to drive competitive advantage, revenue and market share

2. Recommends investment decisions for new product development

3. Conducts abstract competitive analysis for specific products or product lines.

4. Assists with abstract pricing strategies to build and protect a leadership position in market share while enhancing profit margins and developing marketing tools for successful product introductions

5. Partners with Engineering, Manufacturing and Sales to develop new products and enhance existing products as well as communicate critical market needs and time requirements

6. Understands technical and business environments. Assists with the development of strategies to meet business objectives

7. Manages release of abstract products through the end of their product life cycle


Tenure requirements:

1. Rich experience in consumer and industrial ASIC marketing is a must.      

2. Regarded as the technical expert in their particular field

3. Demonstrates in-depth and/or breadth of expertise in own discipline and broad knowledge of other disciplines within the function

4. Anticipates business and regulatory issues; recommends product, process or service improvements

5. Leads projects with notable risk and complexity; develops the strategy for project execution

6. Solves unique and complex problems with broad impact on the business; requires conceptual and innovative thinking to develop solutions

7. Impacts the direction and resource allocation for program, project or services; works within general functional policies and industry guidelines

8. Communicates complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view

address:218, Building 5, 3000 Longdong Road, Pudong New District, Shanghai, China +86 21 5077 3678